The invention generally pertains to dynamic logic pipelines, and more specifically, to a transparent data-triggered latch for use in a dynamic logic pipeline employing vector logic and dynamic logic gates.
Dynamic logic gates are used in the conventional design of logic circuits which require high performance and modest size (pipelines are an example of such a circuit). Dynamic logic gates are much faster than static logic gates. Essentially, a dynamic logic gate is a circuit which requires a periodic electrical precharge, or refresh, in order to maintain and properly perform its intended logic function. Once the electrical precharge on the dynamic logic gate has been discharged, the dynamic logic gate can perform no other logic functions until subsequently precharged.
As described in the U.S. Patent of Yetter entitled "Universal Pipeline Latch for Mousetrap Logic Circuits", U.S. Pat. No. 5,392,423, the speed of dynamic logic pipelines may be improved by latching the data piped into each of the pipeline's logic stages. Yetter teaches a pipeline which uses vector logic and comprises dynamic mousetrap logic gates. A pipeline latch or latches is associated with each logic stage of the pipeline. Each pipeline latch has a latch reset mechanism, an input trigger mechanism, a disabling mechanism, a flip-flop mechanism, an output gating mechanism, and a latch enable pull-up mechanism. The logic stages of the pipeline are alternately clocked. Thus, while the even numbered stages are receiving a high clock signal for instigating propagation of data, the odd numbered stages are receiving a low clock signal for instigating a logic precharge, and vice versa. As a result, the precharging of logic does not detract from the pipeline's operation.
The high and low clock times for each stage of Yetter's pipeline are designed to be substantially equivalent, but due to inherent manufacturing inequalities, clock asymmetry results. Clock asymmetry creates advantaged and disadvantaged clock phases. However, due to Yetter's pipeline latches, pipeline stages operating in a disadvantaged phase can steal time from those operating in an advantaged phase.
U.S. Pat. No. 5,392,423 to Yetter is hereby incorporated by reference for all that it discloses.
Although Yetter's pipeline increases pipeline efficiency by using rising and falling clock edges as triggers, there may be instances wherein valid data is held in limbo while a pipeline stage waits for the next clock edge. That is to say, situations can arise wherein it is advantageous to propagate data to a next logic stage before the next logic stage receives a clock trigger.
It is therefore a primary object of this invention to provide a pipeline latch which has data-triggered outputs, thereby enabling data to be driven when valid, rather than upon receipt of a clock edge.
It is a further object of this invention to provide a pipeline latch which is transparent, thereby enabling data to be stored with essentially no impact on circuit timing.
It is yet another object of this invention to provide a pipeline latch which allows useful work to be done in that time which exists between the storage of valid data, and a clock edge's enablement of a downstream logic stage.